Student Work
Improved Mode S receiver for air traffic control
PublicThis project was done in conjunction with MIT Lincoln Laboratory to upgrade the Air Traffic Control System's Mode S secondary radar (MSSR). The group designed a digital down-converter (DDC) and a monopulse processor, two portions of the Mode S radar receiver, on a field programmable gate array (FPGA). The FPGA uses programmable architecture available from Xilinx and has approximately 3 million gates. Each DDC occupied only 3% of the FPGA's resources and the monopulse processor occupied 14%.
- This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
- Creator
- Publisher
- Identifier
- 03D020M
- Advisor
- Year
- 2003
- Center
- Sponsor
- Date created
- 2003-01-01
- Resource type
- Major
- Rights statement
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Permanent link to this page: https://digital.wpi.edu/show/k35697489