This paper presents a mostly digital Voltage-Controlled-Oscillator(VCO)-based Analog-to-Digital Converter (ADC) with digital background calibration. “Split ADC” architecture containing two channels is utilized for the calibration technique. In each split ADC channel, two equivalent pseudo-differential VCOs are used to construct a differential system to alleviate the even order distortions, and a lookup-table based digital correction with 1st order interpolation is implemented in the ADC's backend for distortions and noise improvement. The proposed ADC combining VCOs and digital calibration engine simplifies the analog design procedure and takes advantage of scaling of CMOS to nanometer dimension. Simulation results in a 65 nm CMOS process targeting 13-b resolution achieves 12.5-b ENOB. DNL and INL are both within 1 LSB.

Creator

• Gong, Jianping
• Li, Sulin
• McNeill, John A.

Publisher

• IEEE

Year

• 2018

Resource type

• Conference Proceeding

Event

• 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) [Montreal, QC, Canada]

Extent

• 5 pages

Rights statement

• In Copyright

Access rights

• © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Citation

• S. Li, J. Gong and J. A. McNeill, "VCO-Based ADC With Digital Background Calibration in 65nm CMOS," 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, QC, Canada, 2018, pp. 195-199, doi: 10.1109/NEWCAS.2018.8585486.

Last modified

• 2024-01-07