This paper presents a Delay-Locked-Loop (DLL) using a low-jitter design technique to generate sub-picosecond-jitter interleaved ADC sampling clock phases. To mitigate the effects of jitter accumulation, a low jitter delay line with digital control circuit is proposed. After 10 delay stages, the proposed DLL output can achieve <;0.1psrms jitter clock. The DLL can operate with input clock frequency from 2GHz to 10GHz, enabling interleaved ADC sampling with a low-jitter sample clock over a 20GHz to 100GHz frequency range.

Creator

• Li, Sulin
• Gong, Jianping
• McNeill, John A.

Publisher

• IEEE

Year

• 2016

Resource type

• Conference Proceeding

Event

• 2016 IEEE International Symposium on Circuits and Systems (ISCAS) [Montreal, QC, Canada]

Extent

• 4 pages

Rights statement

• In Copyright

Access rights

• © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Citation

• J. Gong, S. Li and J. A. McNeill, "Sub-picosecond-jitter clock generation for interleaved ADC with Delay-Locked-Loop in 28nm CMOS," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 2016, pp. 2763-2766, doi: 10.1109/ISCAS.2016.7539165.

Last modified

• 2024-01-05