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12b 100MSps Pipeline ADC with Open-Loop Residue Amplifier

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The design of a low-power 12-bit 100MSps pipeline analog-to-digital converter (ADC) with open-loop residue amplification using the novel "Split-ADC" architecture is described. The choice of a 12b 100MSps specification targets medical applications such as portable ultrasound. For a representative ADC such as the ADS5270, the figure of merit (FOM) is approximately 1pJ/step and the power dissipation is 113mW. The use of an open-loop residue amplifier resulted in a FOM of 0.571pJ/step and a power dissipation of 11.2mW.

  • This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
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  • 2021-01-07
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  • E-project-020708-124929
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Year
  • 2008
Date created
  • 2008-02-07
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Permanent link to this page: https://digital.wpi.edu/show/s4655j244