The design of a low-power 12-bit 100MSps pipeline analog-to-digital converter (ADC) with open-loop residue amplification using the novel "Split-ADC" architecture is described. The choice of a 12b 100MSps specification targets medical applications such as portable ultrasound. For a representative ADC such as the ADS5270, the figure of merit (FOM) is approximately 1pJ/step and the power dissipation is 113mW. The use of an open-loop residue amplifier resulted in a FOM of 0.571pJ/step and a power dissipation of 11.2mW.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Auclair, Devin P
• Gammal, Charles A
• Huang, Fitzgerald J

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-020708-124929

Advisor

• McNeill, John A.

Year

• 2008

Date created

• 2008-02-07

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright

Zuletzt geändert

• 2021-01-07