The primary goal of this project is to identify the fiberflow paradigm of processor organization as a new model for the design of high performance CPUs. The fiberflow model incorporates a number of concepts aimed at maximizing the average instruction throughput rate achievable by the processor, such as on-chip multithreading and data access/execution decoupling. To test the suitability of this approach a prototype fiberflow architecture was defined and simulated.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Tana, Daniel Joseph

Publisher

• Worcester Polytechnic Institute

Identifier

• 02B035M

Advisor

• Ciaraldi, Michael J.

Year

• 2002

Date created

• 2002-01-01

Resource type

• Major Qualifying Project

Major

• Computer Science

Rights statement

• In Copyright