The purpose of this project was to design a parallel digital circuit that performs neural network (NN) calculations more efficiently than traditional software implementations, by taking advantage of the NN's inherent parallel structure. User interfaces for NN training and testing were developed. Tic-Tac-Toe position evaluation was used as a test domain. Testing showed that the parallel hardware NN decreased the number of required clock cycles by an order of magnitude.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Mann, Stephen Robert
• Netsch, Matthew Allenson

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-050310-150502

Advisor

• Bitar, Stephen John
• Brown, David C.

Year

• 2010

Date created

• 2010-05-03

Resource type

• Major Qualifying Project

Major

• Computer Science
• Electrical & Computer Engineering

Rights statement

• In Copyright