Student Work
Design of an Arbiter for DDR3 Memory
PublicDownloadable Content
open in viewerA regular RAM module is designed for use with one system. This project designed a memory arbiter in Verilog that allows for more than one system to use a single DDR3 RAM module in a controlled manner. The arbiter uses fixed priority scheme with an additional timeout feature to avoid starvation. The design was verified in simulation and validated on a Xilinx ML605 evaluation board with a Virtex-6 FPGA.
- This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
- Creator
- Contributors
- Publisher
- Identifier
- E-project-042513-153905
- Advisor
- Year
- 2013
- Sponsor
- Date created
- 2013-04-25
- Resource type
- Major
- Rights statement
Relations
- In Collection:
Items
Items
Thumbnail | Title | Visibility | Embargo Release Date | Actions |
---|---|---|---|---|
TeradyneMQPFinalReport.pdf | Public | Download |
Permanent link to this page: https://digital.wpi.edu/show/2514nn27p