TY - THES A1 - Freeman, Andre A2 - Servatius, Brigitte AB - A Dual-Eulerian graph is a plane multigraph G that contains an edge list which is simultaneously an Euler tour in G and an Euler tour in the dual of G. Dual-Eulerian tours play an important role in optimizing CMOS layouts of Boolean functions. When circuits are represented by undirected multigraphs the layout area of the circuit can be optimized through finding the minimum number of disjoint dual trails that cover the graph. This paper presents an implementation of a polynomial time algorithm for determining whether or not a plane multigraph is Dual-Eulerian and for finding the Dual-Eulerian trail if it exists. DA - 2003/04/30 DB - Digital WPI DP - Worcester Polytechnic Institute ID - etd-0430103-155731 KW - VLSI KW - Dual Eulerian Graphs L1 - https://digital.wpi.edu/show/8w32r567v LA - English LK - https://digital.wpi.edu/ PB - Worcester Polytechnic Institute PY - 2003 T1 - Dual-Eulerian Graphs with Applications to VLSI Design UR - https://digital.wpi.edu/show/z316q165r ER -