Hardware Simulation of Embedded Software Fault Attacks: How to SimpliFI Processor Fault Vulnerability Evaluation

Grycel, Jacob T.

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Hardware Simulation of Embedded Software Fault Attacks: How to SimpliFI Processor Fault Vulnerability Evaluation

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Physical attacks on hardware are increasingly becoming a major consideration in the design of embedded and digital systems. Although side-channel analysis attacks are generally understood, even in complex embedded processors, embedded software vulnerabilities to fault attacks are hard to predict. Despite knowing general behaviors that may be caused by fault attacks, the multiple levels of abstraction between software and the physical hardware make it challenging to predict precisely how a piece of software will respond to fault injection attacks. Current fault evaluation methodologies are split along the hardware/software divide, with hardware fault analysis techniques focusing on simulating all possible faults with no ties to the software, and software simulation methods trading physical accuracy for software state tracking. As a result, the burden of collecting realistic data on software fault vulnerabilities falls on physical device tests, missing the goal of performing fault evaluation during the hardware design cycle. This thesis presents SimpliFI, a methodology for evaluating software fault vulnerabilities and exploring their root causes with realistic fault behavior captured at the hardware level. SimpliFI captures software-level fault effects by simulating instructions being executed by the processor, and hardware-level fault propagation by observing gate-level hardware simulation data. This simulation framework is first defined using broad requirements in order to be applicable to a wide range of devices, and then implemented for a RISC-V embedded processor. The results collected using SimpliFI provide insight into the root cause of software instruction fault responses, and determine realistic faulty outputs of attacks on larger applications.

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