Jitter in Oscillators with 1/f Noise Sources and Application to True RNG for Cryptography

Liu, Chengxin

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Jitter in Oscillators with 1/f Noise Sources and Application to True RNG for Cryptography

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In the design of voltage-controlled oscillators (VCOs) for communication systems, timing jitter is of major concern since it is the largest contributor to the bit-error rate. The latest deep submicron processes provide the possibility of higher oscillator speed at the cost of increased device noise and a higher 1/f noise corner. Therefore it is crucial to characterize the upconverted 1/f noise for practical applications.<BR><BR> This dissertation presents a simple model to relate the time domain jitter and frequency domain phase noise in the presence of non-negligible 1/f noise sources. It will simplify the design, simulation, and testing of the PLL, since with this technique only the open loop VCO needs to be considered. Design methodologies for white noise dominated ring oscillators and PLLs are also developed by analyzing the upconverted thermal noise in time domain using a LTI model. The trade-off and relationship between jitter, speed, power dissipation and VCO geometry are evaluated for different applications. This model is supported by the measured data from 24 ring oscillators with different geometry fabricated in TSMC 0.18um process.<BR><BR> The theory developed in this dissertation is applied to the design of PLL- and DLL- based true random number generators (TRNG) for application in the area of ""smart cards"". New architectures of dual-oscillator sampling and delay-line sampling are proposed for random number generation, which has the advantage of lower power dissipation and lower cost over traditional approaches. Both structures are implemented in test chips fabricated in AMI 1.5um process. The PLL-based TRNG passed the NIST SP800-22 statistical test suite and the DLL-based TRNG passed both the NIST SP800-22 statistical test suite and the Diehard battery of tests.

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