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Split Non-Linear Cyclic Analog-to-Digital Converter Public

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Analog-to-Digital Converters (ADC’s) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC’s linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively loaded differential pair to achieve this gain. The design reduces die size, power usage, and analog complexity. To correct for this inherent non- linearity, a Split ADC concept is employed to enable digital background calibration and a correction algorithm to account for this non- linearity. The Integrated circuit is designed, laid out, and simulated using the Cadence Integrated Circuit Front to Back design suite (ICFB) in the 0.18um Jazz CMOS process.

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  • English
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  • etd-042610-232248
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  • 2010
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  • 2010-04-26
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