In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated.

Creator

• Crasso, Anthony

贡献者

• McNeill, John A.
• Bitar, Stephen J.
• Brown D. Richard, III

Degree

• MS

Unit

• Electrical & Computer Engineering

Publisher

• Worcester Polytechnic Institute

Language

• English

Identifier

• etd-011013-081923

关键词

• ADC
• Calibration
• Flash

Advisor

• McNeill, John A.

Committee

• Brown D. Richard, III
• Bitar, Stephen J.

Defense date

• 2013-01-08

Year

• 2013

Date created

• 2013-01-10

Resource type

• Thesis

Rights statement

• In Copyright