Hardware engineers frequently create formal specification documents as part of the verification process. Doing so is a time-consuming and error-prone process, as the primary documents for communications and standards use a mixture of prose, diagrams and tables. We would like this process to be partially automated, in which the engineer’s role would be to refine a machine-generated skeleton of a specification’s formal model. We have created a preliminary intermediate language which allows specifications to be captured using formal semantics, and allows an engineer to easily find, understand, and modify critical portions of the specification. We have converted most of ARM’s AMBA AHB specification to our language; our representation is able to follow the structure of the original document.

Creator

• Freitas, Paul Michael

Contributors

• Fisler, Kathryn

Degree

• MS

Unit

• Computer Science

Publisher

• Worcester Polytechnic Institute

Language

• English

Identifier

• etd-042908-140922

Keyword

• hardware verification
• timing diagrams
• language
• aspect-oriented programming

Advisor

• Fisler, Kathryn

Defense date

• 2008-05-05

Year

• 2008

Date created

• 2008-04-29

Resource type

• Thesis

Rights statement

• In Copyright

Last modified

• 2020-11-23