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hardware accelerator
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FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography
Keyword:
hardware accelerator
,
FPGA
,
digital signal processing
, and
SVD
Creator:
Coyne, Jack W
Advisor:
Duckworth, R. James
Publisher:
Worcester Polytechnic Institute
Date Created:
2007-09-05
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Electrical & Computer Engineering
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Masters Theses
1
Year
2007
1
Creator
Coyne, Jack W
1
Advisor
Duckworth, R. James
1
Contributor
Cyganski, David
1
Duckworth, R. James
1
Orr, John
1
Unit (Department)
Electrical & Computer Engineering
1
Publisher
Worcester Polytechnic Institute
1
Resource type
Thesis
1
