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Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter

Mot-clé:

Jitter, Clock Generation, Delay Line, Delay-Locked Loop, and Interleaved ADC

Créateur:

Gong, Jianping

Advisor:

McNeill, John A.

Éditeur:

Worcester Polytechnic Institute

date créée:

2019-08-08

Resource Type:

Dissertation

Degree:

PhD

Unit (Department):

Electrical & Computer Engineering