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筛选: 关键词 CDCL

FPGA Accelerated SAT Solver

关键词:

Boolean SAT, FPGA, MQP, Look Up Table, and CDCL

创造者:

Mao, Xinyun, David, Samuel, Eben, Joshua, and Hunter, Patrick

Advisor:

Doroz, Yarkin and Mus, Koksal

出版者:

Worcester Polytechnic Institute

创建日期:

2024-04-25

Resource Type:

Major Qualifying Project