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Filtering by: Creator Feng, Yu Unit (Department) Computer Science

Disjunction of Regular Timing Diagrams

Keyword:

disjunction, timing diagrams, model checking, temporal logic, and Alloy

Creator:

Feng, Yu

Advisor:

Fisler, Kathryn

Publisher:

Worcester Polytechnic Institute

Date Created:

2010-10-12

Resource Type:

Thesis

Degree:

MS

Unit (Department):

Computer Science