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Coyne, Jack W
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FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography
Parola chiave:
hardware accelerator
,
FPGA
,
digital signal processing
, and
SVD
Creatore:
Coyne, Jack W
Advisor:
Duckworth, R. James
Editore:
Worcester Polytechnic Institute
data di creazione:
2007-09-05
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Electrical & Computer Engineering
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Masters Theses
1
Year
2007
1
Creatore
Coyne, Jack W
[remove]
1
Advisor
Duckworth, R. James
1
Contributor
Cyganski, David
1
Duckworth, R. James
1
Orr, John
1
Unit (Department)
Electrical & Computer Engineering
1
Editore
Worcester Polytechnic Institute
1
Tipo di risorsa
Thesis
1