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Filtern nach: Contributor Eisenbarth, Thomas Stichwort cross-core

Implicit Cache Lockdown on ARM: An Accidental Countermeasure to Cache-Timing Attacks

Stichwort:

cache-timing, cross-core, cache, ARM, Security, Countermeasure, lockdown, and side-channel

Schöpfer:

Green, Marc

Advisor:

Eisenbarth, Thomas

Herausgeber:

Worcester Polytechnic Institute

Datum erstellt:

2017-01-20

Resource Type:

Thesis

Degree:

MS

Unit (Department):

Computer Science