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Eisenbarth, Thomas
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Year
2017
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Threshold Implementations of the Present Cipher
Keyword:
Cryptography
,
Masking
,
Threshold implementation
,
Countermeasure
,
Present cipher
,
FPGA
,
Side channel countermeasure
, and
Lightweight cryptography
Creator:
Farmani, Mohammad
Advisor:
Eisenbarth, Thomas
Publisher:
Worcester Polytechnic Institute
Date Created:
2017-09-06
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Electrical & Computer Engineering
Side-Channel Attacks on Intel SGX: How SGX Amplifies The Power of Cache Attack
Keyword:
trusted execution environment
,
side-channel
,
Attack
,
SGX
,
cache attack
,
Security
,
Cryptography
,
key recovery
,
AES
,
TEE
,
T-Table
, and
cache
Creator:
Moghimi, Ahmad
Advisor:
Eisenbarth, Thomas
Publisher:
Worcester Polytechnic Institute
Date Created:
2017-04-27
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Computer Science
Efficient Side-channel Resistant MPC-based Software Implementation of the AES
Keyword:
multiparty computation
,
AES
,
polynomial masking
, and
side-channel analysis
Creator:
Fernandez Rubio, Abraham
Advisor:
Eisenbarth, Thomas
Publisher:
Worcester Polytechnic Institute
Date Created:
2017-04-27
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Electrical & Computer Engineering
Cross-core Microarchitectural Attacks and Countermeasures
Keyword:
Side Channel Attacks
,
Microarchitectural attacks
, and
cache attacks
Creator:
Irazoki, Gorka
Advisor:
Eisenbarth, Thomas
Publisher:
Worcester Polytechnic Institute
Date Created:
2017-04-24
Resource Type:
Dissertation
Degree:
PhD
Unit (Department):
Electrical & Computer Engineering
Implicit Cache Lockdown on ARM: An Accidental Countermeasure to Cache-Timing Attacks
Keyword:
cache-timing
,
cross-core
,
cache
,
ARM
,
Security
,
Countermeasure
,
lockdown
, and
side-channel
Creator:
Green, Marc
Advisor:
Eisenbarth, Thomas
Publisher:
Worcester Polytechnic Institute
Date Created:
2017-01-20
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Computer Science
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Eisenbarth, Thomas
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